Integrated circuit devices having dual data rate (DDR) capability can support generating output data on both the rising and falling edges of a clock signal. This means that data can be generated at twice the rate of the clock signal frequency. FIG. 1 is a block diagram showing a conventional DDR semiconductor device 100. Referring to FIG. 1, the DDR semiconductor device 100 includes a core block 110, a data output circuit 120, and a data output pad 130. Data D0 and D1 are read from the core block 110. The core block 110 is a memory core block when the semiconductor device 100 is a memory device and may include a processor when the semiconductor device 100 is a memory controller. The two bits of data D0 and D1 read in parallel from the core block 110 are multiplexed by the data output circuit 120, and the multiplexed data DOUT is output to the outside through one of the data output pads 130. Here, the output pad 130 may be a pad used for both inputting and outputting data.
FIG. 2 is a block diagram of the data output circuit 200 according to a prior art. Referring to FIG. 2, the data output circuit 200 includes two flip-flop 121, 122, and a multiplexer 123. A first flip-flop 121 receives one of the data (a first data, D0) between two parallel data D0 and D1, and outputs a first data DA in response to a rising edge of a clock signal CLK. A second flip-flop 122 receives another data (a second data, D1) out of two parallel data D0 and D1, and outputs a second data DB in response to the rising edge of the clock signal CLK. The multiplexer 123 selects and outputs the output data DA of the first flip-flop when the clock signal CLK is a high level, and selects and outputs the output data DB of the second flip-flop when the clock signal CLK is a low level.
FIG. 3 is a signal timing diagram of the data output circuit 200 illustrated in FIG. 2. Here, it is supposed that (D0, D1) is (1,0). The first data D0 is output to a first node N1 after a clock-Q delay TCLK-Q from the rising edge timing point 0 of the clock signal CLK. The clock-Q delay TCLK-Q is a time from the rising edge timing point of the clock signal CLK input to the flip-flop until the data is output to a Q terminal of the flip-flop. As the data DA output to the first node N1 is output through the multiplexer 123, the output data DOUT occurs after a delay time of the multiplexer 123, a multiplexer delay TMUX. Therefore, the first data D0 is output as the output data DOUT after the clock-Q delay plus the multiplexer delay (i.e., TCLK-Q plus TMUX). On the other hand, as the second data D1 output to the second node N2 is output through the multiplexer 123, it is output as the output data DOUT after the multiplex delay TMUX from a falling edge timing point 1 of the clock signal CLK. Therefore, a duty of the output data DOUT when the clock signal CLK is high level in a first clock cycle from 0 to 2 (i.e., the duty of the output data DOUT when the duty in a high-level period by the first data D0) is TP/2−TCLK-Q but the duty of the output data DOUT when the clock signal CLK is a low level (i.e. the duty in a low-level period by the second data D1) becomes TP/2, which causes the duty of two data to become different.
These distortions of the data duty result in a decreasing timing margin. In particular, the duty and a skew of the data become a more important issue when the operating frequency becomes higher. Therefore, the data duty of the data output circuit in a DDR mode needs to be improved to increase the reliability of high frequency semiconductor devices.